硅模具(PDMS芯片模具)是制备高深宽比PDMS芯片微通道的理想选择,利用硅的干法刻蚀技术,可以轻松实现深宽比最高达25:1的微通道结构,而且线条宽度可控制在2微米以上,精度误差仅在±1微米范围内。
然而,硅表面通常具有强烈的亲水性,这可能导致PDMS chip在脱模时黏附在硅表面,制造过程中的一大挑战。
为解决这个问题,通常需要对硅表面进行疏水修饰,使硅表面变得疏水,确保PDMS chipfrom the silicon mold, free from interference caused by hydrophilicity (specific hydrophobic solutions can be consulted with the sales team).
在制备PDMS芯片过程中,为了实现高深宽比的结构,通常采用的PDMS芯片模具是硅模具,硅模具是通过硅的干法刻蚀技术直接在硅表面加工出高深宽比的结构,在这一领域的领军者之一,德国斯图加特的Robert Bosch GmbH,提出了一项专利的DRIE方法,通过在高频电感耦合等离子体反应离子蚀刻(ICP-RIE)系统中交替执行蚀刻和沉积步骤,实现了高效而精密的微纳加工。
具体而言,该方法包括薄膜沉积、底部薄膜蚀刻和硅蚀刻三个关键步骤。在沉积工艺中,钝化膜被沉积在沟槽的侧壁和底面,而在底部膜蚀刻步骤中,通过选择性蚀刻沟槽底部上的钝化膜,实现了微结构的精细控制。最后,在硅蚀刻步骤中,仅蚀刻已去除钝化膜的沟槽底部的硅,进一步细化加工效果。
蚀刻过程中,垂直取向的离子(SFx+)起到了至关重要的作用,通过增强氟自由基,有效地去除了沟槽底部沉积的钝化膜,同时保持了薄膜沿侧壁的相对完整性。
蚀刻产生的侧壁纹理受到配方的影响,呈现出不同程度的扇形。值得注意的是,DRIE蚀刻速率随着沟槽深宽比的增加而降低,这为实现更加复杂的微结构提供了挑战。
The strong hydrophilicity of the silicon mold surface in the PDMS chip preparation process can lead to adhesion issues, presenting a significant challenge in manufacturing. To address this problem, it is common to perform hydrophobic modification on the silicon mold surface, changing its surface properties to exhibit hydrophobicity, reducing adhesion with the PDMS chip. Surface hydrophobic modification of silicon is a complex and critical step involving various surface treatment techniques.
One commonly used method for hydrophobic modification of PDMS chip molds is through the formation of Self-Assembled Monolayers (SAMs). SAMs consist of a self-assembled structure of a monolayer of organic molecules, forming a hydrophobic protective layer on the silicon surface. Typically chosen organic molecules include long-chain alkanes or aromatic molecules, where the hydrophobic tails bind to the silicon surface, exposing hydrophilic heads on the surface, altering the chemical properties of the silicon surface.
Another common method for hydrophobic modification of PDMS chip molds is Chemical Vapor Deposition (CVD). Through CVD, a thin film is formed on the silicon surface, usually made of materials such as hydrogenated amorphous silicon or tetrahydrofuran derivatives, inducing a chemical change on the silicon surface, rendering it hydrophobic. This method offers high controllability and allows precise hydrophobic regulation of the silicon surface.
此外,等离子体辅助化学气相沉积(Plasma-Assisted Chemical Vapor Deposition,PACVD)也是一种有效的硅表面疏水修饰方法。
在等离子体的作用下,气相中的前体分子发生解离并沉积在硅表面,形成疏水性的薄膜。等离子体的存在使得沉积的薄膜更加致密和均匀,提高了修饰效果。
这些硅模具表面疏水修饰方法不仅可以防止PDMS芯片与硅表面的黏附,还可以提高芯片的耐久性和稳定性。
疏水修饰的硅表面在制备过程中有效减少了模具与芯片之间的粘附力,简化了脱模步骤,提高了制备效率。
通过选择合适的疏水修饰方法,可以根据实际需求对硅表面进行定制化处理,为PDMS芯片的制备提供了更灵活和可控的解决方案。
硅表面疏水修饰技术的发展不仅推动了微流控芯片制备工艺的进步,也在其他领域的材料科学和微纳加工中展现出广泛的应用前景。
> Processing Technology: Deep Silicon Etching
> Line Width: ≥2 μm
> Aspect Ratio: Maximum 25:1
> Processing Accuracy: ±1 μm
> Surface Treatment: Hydrophobic Treatment
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